1. Field of the Invention
The invention relates to a method for fabricating a memory device, and more particularly to a method of forming a negative capacitance (NC) insulating layer between floating gate and control gate of the memory device.
2. Description of the Prior Art
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased electrically.
Product development efforts in memory device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Some of the flash memory arrays today utilize a gate structure made of dual polysilicon layers (also refers to as the dual poly-Si gate). The polysilicon layer utilized in these gate structures often includes a dielectric material composed of an oxide-nitride-oxide (ONO) structure. When the device is operating, electrons are injected from the substrate into the bottom layer of the dual polysilicon layers for storing data. Since these dual gate arrays typically store only one single bit of data, they are inefficient for increasing the capacity of the memory. As a result, a flash memory made of silicon-oxide-nitride-oxide-silicon (SONOS) is derived. Preferably, a transistor from these memories is capable of storing two bits of data simultaneously, which not only reduces the size of the device but also increases the capacity of the memory significantly.
Despite the common utilization of these devices, current flash memory devices normally require high voltages in operations such as programming and erasing. Although VDD of logic device scales, the operation voltage of flash memory does not. Hence, how to improve the current fabrication process for resolving this issue has become an important task in this field.